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ADE7518
Table 8. SPI Slave Mode Timing (SPICPHA = 1) Parameters
Parameter
Description
Min
Typ
Max
Unit
t SS
t SL
t SH
t DAV
t DSU
t DHD
t DF
t DR
t SR
t SF
t SFS
SS to SCLK edge
SCLK low pulse width
SCLK high pulse width
Data output valid after SCLK edge
Data input setup time before SCLK edge
Data input hold time after SCLK edge
Data output fall time
Data output rise time
SCLK rise time
SCLK fall time
SS high after SCLK edge
145
6 × t CORE1
6 × t CORE1
0
2 × t CORE1 + 0.5
0
19
19
19
19
25
ns
ns
ns
ns
ns
μs
ns
ns
ns
ns
ns
1
t CORE depends on the clock divider or CD[2:0] bits of the POWCON SFR (see Table 24); t CORE = 2 CD /4.096 MHz.
SS
t SS
t SFS
SCLK
(SPICPOL = 0)
t SH
t SL
SCLK
(SPICPOL = 1)
t SR
t SF
t DAV
t DF
t DR
MISO
MOSI
MSB
MSB IN
t DSU
t DHD
BITS [6:1]
BITS [6:1]
LSB
LSB IN
Figure 6. SPI Slave Mode Timing (SPICPHA = 1)
Rev. 0 | Page 12 of 128
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